technical data 274 presettable bcd/decade up/down counter high-speed silicon-gate cmos the in74ac192 is identical in pinout to the ls/als192, hc/hct192. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/als outputs. the counter has two separate clock inputs, a count up clock and count down clock inputs. the direction of counting is determined by which input is clocked. the outputs change state synchronous with the low-to-high transitions on the clock inputs. this counter may be preset by entering the desired data on the p0, p1, p2, p3 input. when the parallel load input is taken low the data is loaded independently of either clock input. this feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. in addition the counter can also be cleared. this is accomplished by inputting a high on the master reset input. all 4 internal stages are set to low independently of either clock input.both a terminal count down (tc d ) and terminal count up (tc u ) outputs are provided to enable cascading of both up and down counting functions. the tc d output produces a negative going pulse when the counter underflows and tc u outputs a pulse when the counter overflows. the counter can be cascaded by connecting the tc u and tc d outputs of one device to the count up clock and count down clock inputs, respectively, of the next device. ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a, 0.1 a @ 25 c ? high noise immunity characteristic of cmos devices ? outputs source/sink 24 ma in74ac192 ordering information IN74AC192N plastic in74ac192d soic t a = -40 to 85 c for all packages pin assignment logic diagram pin 16 =v cc pin 8 = gnd
in74ac192 275 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t j junction temperature (pdip) 140 c t a operating temperature, all package types -40 +85 c i oh output current - high -24 ma i ol output current - low 24 ma t r , t f input rise and fall time * (except schmitt inputs) v cc =3.0 v v cc =4.5 v v cc =5.5 v 0 0 0 150 40 25 ns/v * v in from 30% to 70% v cc this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74ac192 276 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limits symbol parameter test conditions v 25 c-40 c to 85 c unit v ih minimum high-level input voltage v out =0.1 v or v cc -0.1 v 3.0 4.5 5.5 2.1 3.15 3.85 2.1 3.15 3.85 v v il maximum low -level input voltage v out =0.1 v or v cc -0.1 v 3.0 4.5 5.5 0.9 1.35 1.65 0.9 1.35 1.65 v v oh minimum high-level output voltage i out -50 a 3.0 4.5 5.5 2.9 4.4 5.4 2.9 4.4 5.4 v * v in =v ih or v il i oh =-12 ma i oh =-24 ma i oh =-24 ma 3.0 4.5 5.5 2.56 3.86 4.86 2.46 3.76 4.76 v ol maximum low-level output voltage i out 50 a 3.0 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v * v in =v ih or v il i ol =12 ma i ol =24 ma i ol =24 ma 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 i in maximum input leakage current v in =v cc or gnd 5.5 0.1 1.0 a i old +minimum dynamic output current v old =1.65 v max 5.5 75 ma i ohd +minimum dynamic output current v ohd =3.85 v min 5.5 -75 ma i cc maximum quiescent supply current (per package) v in =v cc or gnd 5.5 8.0 80 a * all outputs loaded; thresholds on input associated with output under test. +maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc function table inputs mode mr pl cp u cp d hx x x reset(asyn.) l l x x preset(asyn.) l h h no count l h h count up l h h count down l h h no count x = don?t care the in74ac192 can be preset to any state, but will not count beyond 9. if preset to state 10, 11, 12, 13, 14 or 15, it will follow the sequence 10, 11, 6: 12, 13, 4: 14, 15, 2 if counting up, and follow the sequence 15, 14, 13, 12, 11, 10, 9 if counting down. logic equations for terminal count: tc u = q 0 ? q 3 ? cp u tc d = q 0 ? q 1 ? q 2 ? q 3 ? cp d
in74ac192 277 ac electrical characteristics (c l =50pf,input t r =t f =3.0 ns) v cc * guaranteed limits symbol parameter v 25 c-40 c to 85 c unit min max min max f max maximum clock frequency (figure 1) 3.3 5.0 88 120 40 55 mhz t plh propagation delay, cp u or cp d to tc u or tc d (figure 2) 3.3 5.0 20 13 22 14.5 ns t phl propagation delay, cp u or cp d to tc u or tc d (figure 2) 3.3 5.0 19 11.5 21 13.0 ns t plh propagation delay, cp u or cp d to q n (figure 1) 3.3 5.0 15 10 17.0 11.5 ns t phl propagation delay, cp u or cp d to q n (figure 1) 3.3 5.0 15 9.5 17.0 11 ns t plh propagation delay, p n to q n (figure 3) 3.3 5.0 15 10 17.0 11.5 ns t phl propagation delay, p n to q n (figure 3) 3.3 5.0 15 9.5 17.0 11 ns t plh propagation delay, pl to q n (figure 4) 3.3 5.0 15 10 17 11.5 ns t phl propagation delay, pl to q n (figure 4) 3.3 5.0 20 12.5 22 14 ns t phl propagation delay, mr to q n (figure 5) 3.3 5.0 20 12.5 22 14 ns t plh propagation delay, mr to tc u (figure 6) 3.3 5.0 18 12 20 13.5 ns t phl propagation delay, mr to tc d (figure 6) 3.3 5.0 19 11.5 21 13.0 ns t plh propagation delay, pl to tc u or tc d (figure 6) 3.3 5.0 20 13 22 14.5 ns t phl propagation delay, pl to tc u or tc d (figure 6) 3.3 5.0 15 8.5 17 10 ns t plh propagation delay, p n to tc u or tc d (figure 6) 3.3 5.0 20 13 22 14.5 ns t phl propagation delay, p n to tc u or tc d (figure 6) 3.3 5.0 20 12.5 22 14 ns c in maximum input capacitance 5.0 4.5 4.5 pf typical @25 c,v cc =5.0 v c pd power dissipation capacitance 45 pf * voltage range 3.3 v is 3.3 v 0.3 v voltage range 5.0 v is 5.0 v 0.5 v
in74ac192 278 timing requirements (c l =50pf, input t r =t f =3.0 ns) v cc * guaranteed limits symbol parameter v 25 c-40 c to 85 c unit t su minimum setup time, p n to pl (figure 7) 3.3 5.0 9 6 10 7 ns t h minimum hold time, pl to p n (figure 7) 3.3 5.0 -1.0 -1.0 0 0 ns t w minimum pulse width, pl (figure 4) 3.3 5.0 17 12 21 13 ns t w minimum pulse width, cp u or cp d (figure 1) 3.3 5.0 11 8 12 9 ns t w minimum pulse width, mr (figure 5) 3.3 5.0 14 10 16 12 ns t rec minimum recovery time, pl to cp u or cp d (figure 5) 3.3 5.0 9 12 10 13 ns t rec minimum recovery time, mr to cp u or cp d (figure 5) 3.3 5.0 17 12 21 14 ns * voltage range 3.3 v is 3.3 v 0.3 v voltage range 5.0 v is 5.0 v 0.5 v figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms figure 4. switching waveforms
in74ac192 279 figure 5. switching waveforms figure 6. switching waveforms figure 7. switching waveforms timing diagram
in74ac192 280 expanded logic diagram
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